Nonvolatile ferroelectric memory device and method for detecting weak cell using the same

ABSTRACT

A nonvolatile ferroelectric memory device and a method for detecting a weak cell using the same are provided. The nonvolatile ferroelectric memory device includes: a nonvolatile ferroelectric memory cell driver including a top cell array and a bottom cell array, a sensing amplifier formed between the top and bottom cell arrays for sensing the top and bottom cell arrays, and a wordline driver for driving a wordline of the top and bottom cell arrays; an X-decoder for selectively outputting a wordline decoding signal to the wordline driver; and a pulse width generating unit for varying a width of a restore pulse PW 1  and outputting the varied width to the wordline driver to detect a weak cell of the top and bottom cell arrays.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device,and more particularly, to a nonvolatile ferroelectric memory device andmethod for detecting a weak cell using the same.

[0003] 2. Background of the Related Art

[0004] Generally, a nonvolatile ferroelectric memory, i.e., aferroelectric random access memory (FRAM) has a data processing speedequal to a dynamic random access memory (DRAM) and retains data even inpower off. For this reason, the nonvolatile ferroelectric memory hasreceived much attention as a next generation memory device.

[0005] The FRAM and DRAM are memory devices with similar structures, butthe FRAM includes a ferroelectric capacitor having a high residualpolarization characteristic. The residual polarization characteristicpermits data to be maintained even if an electric field is removed

[0006]FIG. 1 shows hysteresis loop of a general ferroelectric. As shownin FIG. 1, even if polarization induced by the electric field has theelectric field removed, data is maintained at a certain amount (i.e., dand a states) without being erased due to the presence of residualpolarization (or spontaneous polarization). A nonvolatile ferroelectricmemory cell is used as a memory device by corresponding the d and astates to 1 and 0, respectively.

[0007] A related art nonvolatile ferroelectric memory device will now bedescribed. FIG. 2 shows unit cell of a related art nonvolatileferroelectric memory.

[0008] As shown in FIG. 2, the related art nonvolatile ferroelectricmemory includes a bitline B/L formed in one direction, a wordline W/Lformed to cross the bitline, a plate line P/L spaced apart from thewordline the same direction as the wordline, a transistor T1 with a gateconnected with the wordline and a source connected with the bitline, anda ferroelectric capacitor FC1. A first terminal of the ferroelectriccapacitor FC1 is connected with a drain of the transistor T1 and asecond terminal is connected with the plate line P/L.

[0009] In the related art nonvolatile ferroelectric memory includingunit cells, weak cells occur due to defect of the ferroelectriccapacitor of each unit cell.

[0010] To detect such weak cells, an offset sensing amplifying circuitshown in FIG. 3 is typically used. That is, a sensing margin is variedby adding an offset voltage to a sensing voltage of a bit line.

[0011] A method for detecting weak cells using the related artnonvolatile ferroelectric memory will be described with reference to theaccompanying drawings.

[0012]FIG. 3 is a diagram of an offset control circuit of a related artsensing amplifier, and FIG. 4 is a graph showing the variation of anoffset voltage according to a bitline voltage during a reading mode ofthe cell.

[0013] As shown in FIG. 3, the offset control circuit of the related artsensing amplifier includes a bitline, a bitline bar, a first inverter,and a second inverter. The first inverter inverts a bitline signalbetween the bitline and the bitline bar, and the second inverter invertsa bitline bar signal and outputs the inverted signal to the bitline.

[0014] A first switching transistor and a first offset capacitor areprovided between the bitline and a driver while a second switchingtransistor and a second offset capacitor are provided between thebitline bar and the driver.

[0015] At this time, the first switching transistor transmits thebitline signal to the driver through the offset capacitor while thesecond switching transistor transmits the bitline bar signal to thedriver through the offset capacitor.

[0016] The related art method for detecting weak cells is performedusing the offset control circuit shown in FIG. 3. In this method, thesensing margin is varied by adding the offset voltage to the bitlinesensing voltage.

[0017] In other words, addition of an offset to a normal bitline levelbreaks loading balance of the bitline, and an operational margin of asensing amplifier is reduced during sensing operation. Thus, weak cellsare detected.

[0018]FIG. 4 is a graph showing variation of an offset voltage accordingto a bitline voltage during related art reading mode. Referring to FIG.4, if the bitline voltage is small during the reading mode, the offsetvoltage applied to the bitline becomes small. If the bitline voltage isgreat, the offset voltage becomes grater.

[0019] The related art method for detecting weak cells using the relatedart nonvolatile ferroelectric memory has several problems.

[0020] Since a separate offset capacitor is required to detect the weakcells, the process becomes complicated. If the process conditions arevaried, a normal bitline level is varied. This may cause an error indetecting the weak cells.

SUMMARY OF THE INVENTION

[0021] An object of the invention is to solve at least the aboveproblems and/or disadvantages and to provide at least the advantagesdescribed hereinafter.

[0022] Another object of the present invention is to provide anonvolatile ferroelectric memory device and method for detecting a weakcell using the same in which a separate test mode is not required, and aweak cell is easily detected and eliminated even if process conditionsare varied.

[0023] To achieve at least these objects and other advantages in a wholeor in part and in accordance with the purpose of the present invention,as embodied and broadly described, a nonvolatile ferroelectric memorydevice according to the present invention includes: a nonvolatileferroelectric memory cell driver including a top cell array and a bottomcell array, a sensing amplifier formed between the top and bottom cellarrays, for sensing the top and bottom cell arrays, and a wordlinedriver for driving a wordline of the top and bottom cell arrays; anX-decoder for selectively outputting a wordline decoding signal to thewordline driver; and a pulse width generating unit for varying a widthof a restore pulse PW1 and outputting the varied width to the wordlinedriver to detect a weak cell of the top and bottom cell arrays.

[0024] To further achieve the above objects in a whole or in partaccording to the present invention, a method for detecting a weak cellusing a nonvolatile ferroelectric memory device including a nonvolatileferroelectric memory cell driver having a top cell array and a bottomcell array, a sensing amplifier for sensing the top and bottom cellarrays, and a wordline driver for driving a wordline of the top andbottom cell arrays, includes the steps of: selectively outputting awordline decoding signal to the wordline driver; varying a width of arestore pulse PW1 and outputting the restored pulse having a variedwidth to the wordline driver to detect a weak cell of the upper andlower cell arrays; controlling data(charge amount) to be stored in amemory cell of each cell array to correspond to the size of the outputrestore pulse PW1 and outputting bitline sensing levels varied tocorrespond to the size of the restore pulse; and sensing a memory cellthat reaches a minimum sensing level among the varied bitline sensinglevels to determine a weak cell.

[0025] These and other objects of the present application will becomemore readily apparent from the detailed description given hereinafter.However, it should be understood that the detailed description andspecific examples, while indicating preferred embodiments of theinvention, are given byway of illustration only, since various changesand modification within the spirit and scope of the invention willbecome apparent to those skilled in the art from this detaileddescription.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

[0027]FIG. 1 shows hysteresis loop of a general ferroelectric;

[0028]FIG. 2 is a schematic view of a unit cell of a related artnonvolatile ferroelectric memory;

[0029]FIG. 3 is a diagram of an offset control circuit of a related artsensing amplifier;

[0030]FIG. 4 is a graph showing variation of an offset voltage accordingto a bitline voltage during related art reading operation;

[0031]FIG. 5 is a schematic view of a nonvolatile ferroelectric memorydevice according to an embodiment of the present invention;

[0032]FIG. 6 is a schematic view of a memory cell array according to thenonvolatile ferroelectric memory device of FIG. 5;

[0033]FIG. 7 is a circuit diagram of a unit main cell of FIG. 6;

[0034]FIG. 8 is a circuit diagram of a reference cell of FIG. 6;

[0035]FIG. 9 is a timing chart showing the operation of a write modeaccording to an embodiment of the nonvolatile ferroelectric memorydevice of the present invention;

[0036]FIG. 10 is a timing chart showing the operation of a read modeaccording to an embodiment of the nonvolatile ferroelectric memorydevice of the present invention;

[0037]FIG. 11 is a circuit diagram of the pulse width variablecontroller in FIG. 5;

[0038]FIG. 12 is a circuit diagram of the first switching signalgenerator in FIG. 5;

[0039]FIG. 13 is a circuit diagram of the second switching signalgenerator in FIG. 5;

[0040]FIG. 14 is a graph showing dependancy of memory charges accordingto the size of the pulse width PW1;

[0041] FIGS. 15(a)-15(c) show various examples of the pulse width PW1;

[0042]FIG. 16 shows dependancy of a voltage induced to a bitline B/Laccording to variation of the pulse width PW1 in FIG. 15;

[0043]FIG. 17 is a schematic view illustrating the operation of a highvoltage sensing synchronizing circuit in FIG. 5; and

[0044] FIGS. 18(a)-18(d) illustrate the pulse widths PW1 according tosignal waveforms SWC1 and SWC2 of FIG. 17.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0045] Reference will now be made in detail to the preferred embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings.

[0046] In the present invention, it is intended that a weak cell iseliminated in advance to ensure reliability of a nonvolatileferroelectric memory chip. That is, an operational pulse width of a cellis varied to control data to be stored in the cell, so that a bitlinesensing level is varied. A sensing input voltage of a sensing amplifieris varied to allow a weak cell to reach a minimum sensing level, therebyeliminating the weak cell

[0047] A nonvolatile ferroelectric memory device and method fordetecting a weak cell using the same will now be described withreference to the accompanying drawings.

[0048] First, as shown in FIG. 5, the nonvolatile ferroelectric memorydevice of the present invention includes a memory cell array 50, awordline driver 57, an X-decoder 51 for driving the wordline driver 57,and a pulse generator 56 for detecting a weak cell of the memory cellarray 50.

[0049] The memory cell array 50, as shown in FIGS. 5 and 6, includes aplurality of sub cell arrays. A sensing amplifier S/A 120 is formedbetween adjacent top and bottom sub cell arrays sub_T and sub_B.

[0050] As shown in FIG. 6, each of the sub cell arrays includes bitlinesTop_B/L and Bot_B/L, a plurality of main cells MC connected to thebitlines Top_B/L and Bot_B/L, a reference cell RC connected to thebitlines Top_B/L and Bot_B/L, and a column selector CS.

[0051] The reference cell RC within the sub cell array sub_T formed in atop portion of the sensing amplifier S/A is simultaneously accessed whenthe main cell MC within the sub cell array sub_(d—)B is accessed.

[0052] On the other hand, the reference cell RC within the sub cellarray sub_(d—)B formed in a bottom portion of the sensing amplifier S/Ais simultaneously accessed when the main cell MC within the sub cellarray sub T is accessed.

[0053] The column selector CS selectively activates a correspondingcolumn bitline using a Y(column) address.

[0054] If the column selector CS is in high level, the correspondingcolumn bitline is connected to a data bus, so as to enable datatransmission.

[0055] The main cell MC is constructed as shown in FIG. 7. As shown, abitline B/L is formed in one direction, and a wordline W/L is formed tocross the bitline B/L. A plate line P/L is spaced apart from thewordline W/L in the same direction as the worde W/L. A transistor T,with a gate connected with the wordline W/L and a source connected withthe bitline B/L, is formed. A ferroelectric capacitor FC is formed insuch a manner that its first terminal is connected with a drain of thetransistor T and its second terminal is connected with the plate lineP/L.

[0056]FIG. 8 is a detailed schematic view of the reference cell RC ofthe nonvolatile ferroelectric memory device according to an embodimentof the present invention. As shown in FIG. 8, the reference cell RC ofthe nonvolatile ferroelectric memory device includes a bitline B/Lformed in one direction, a reference wordline REF_W/L formed across thebitline, a switching block 81, a level initiating block 82, and aplurality of ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCn.The switching block 81 is controlled by a signal of the referencewordline REF_W/L to selectively transmit a reference voltage stored inthe ferroelectric capacitors to the bitline B/L. The level initiatingblock 82 selectively initiates a level of an input terminal of theswitching block 81 connected to the ferroelectric capacitors. Theferroelectric capacitors are connected to the input terminal of theswitching block 81 in parallel.

[0057] The switching block 81 includes an NMOS transistor (hereinafter,“first transistor”) T1 with a gate connected to the reference wordlineREF W/L, a drain connected to the bitline B/L, and a source connected toa storage node SN.

[0058] The level initiating block 82 is controlled by a reference cellequalizer control signal REF_EQ, which is a control signal forinitiating the storage node SN of the reference cell RC. Also, the levelinitiating block 82 includes an NMOS transistor (hereinafter, “secondtransistor”) T2 connected between the source of the first transistor T1and a ground terminal Vss.

[0059] The ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCninclude a first electrode, a second electrode, and a ferroelectricmaterial formed between first and second electrodes. The first electrodeof each ferroelectric capacitor is connected to the source of the firsttransistor T1, and its second electrode is connected to the referenceplate line REF_P/L.

[0060] The number of the ferroelectric capacitors FC1, FC2, FC3, FC4, .. . , FCn is determined depending on the desired capacitor size of thereference cell. That is, the number of the ferroelectric capacitors canfreely be adjusted depending on the capacitor size of the referencecell.

[0061] The storage node SN is connected with first terminals of theferroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCn in parallel.

[0062] The reference cell equalizer control signal REF_EQ initiates thestorage node SN to a ground voltage level. Namely, if the reference cellequalizer control signal REF_EQ is in high level, the second transistorT2 is turned on so that the storage node SN is maintained at a groundvoltage level.

[0063] The operation of the aforementioned reference cell will now bedescribed. Qs and Qns of the hysteresis loop in FIG. 1 denote switchingcharges of the ferroelectric capacitor and non-switching charges of theferroelectric capacitor, respectively. The reference cell of the presentinvention is based on Qns. That is to say, the reference wordlineREF_W/L within the operation cycle is transited to high level togetherwith the reference plate line REF_P/I. Accordingly, charges equivalentto the size of Qns of the ferroelectric capacitor are supplied to thebitline B/L.

[0064] Then, the reference wordline REF_W/L is transited to low levelbefore the sensing amplifier is operated, so that the reference cell isnot affected by a voltage of the bitline B/L.

[0065] Meanwhile, the reference plate line REF_P/L is maintained at highlevel, and is transited to low level when the reference wordline REF_W/Lis sufficiently stabilized.

[0066] As described above, since non-switching charges Qns are used, aseparate restoring operation is not required during a precharge period.Accordingly, high level is not required any longer in the referencewordline REF_W/L.

[0067] Since the reference level is affected by an initial level of thestorage node SN, the second transistor T2 of FIG. 8 is used to stabilizethe storage node SN, and the reference equalizer control signal REF_EQis used to initiate the storage node SN to the ground voltage level.Therefore, since the initial level of the storage node SN is maintainedat the ground voltage level, the reference level can be stabilized.

[0068] Reading and writing operations of the nonvolatile ferroelectricmemory device according to the present invention will now be described.

[0069]FIG. 9 is a timing chart showing the operation of a write modeaccording to the nonvolatile ferroelectric memory device of the presentinvention, and FIG. 10 is a timing chart showing the operation of a readmode according to the nonvolatile ferroelectric memory device of thepresent invention.

[0070] The write mode and read mode differ from each other in thedirection of the transmission of data. Referring to FIG. 9, externaldata is forcibly input to the bitline B/L through a data input pad whenthe writing operation is performed by a write enable signal WEBpad.During the read operation, referring to FIG. 10, data amplified by thesensing amplifier is transmitted to an external data input/output pad.

[0071] With reference to the waveforms of FIG. 9, the data writingoperation will be described.

[0072] One cycle is completed in such a manner that an external chipenable signal CSBpad is transited to low level to start an active periodand then a precharge period advances.

[0073] If an active period of a chip starts at the beginning of periodA, then address decoding starts during a period A. A correspondingwordline W/L, a corresponding plate line P/L, a corresponding referencewordline REF_W/L, and a corresponding reference plate line REF_P/L areactivated at high levels as various control signals are activated.

[0074] During period B, the wordline W/L and the reference wordlineREF_W/L are maintained at a high level, so that the data of the maincell MC and the data of the reference cell RC are respectivelytransmitted to their bitlines B/L. Also, the main cell has a logic valueof “0” and is amplified in period C.

[0075] For reference, the bitline B/L to which the data of the main cellMC is transmitted is not the same as the bitline B/L to which the dataof the reference cell RC is transmitted. Namely, as described above,among sub cell arrays, the main cell MC within the sub cell array at thetop portion of the sensing amplifier is operated together with thereference cell within the sub cell array at the bottom portion of thesensing amplifier. Accordingly, the data of the main cell is transmittedto the bitline within the sub cell array at the top portion while thedata of the reference cell is transmitted to the bitline within the subcell array at the bottom portion.

[0076] When the data of the main cell and the data of the reference cellare sufficiently transmitted to their corresponding bitline, thewordline W/L and the reference wordline REF_W/L are transited to lowlevel so that the bitline B/L is separated from the cell.

[0077] Therefore, bitline loading due to the difference of the capacitorsize between the main cell and the reference cell can be removed. Thisimproves a sensing margin of the sensing amplifier.

[0078] When the wordline W/L and the reference wordline REF_W/L aretransited to low level, a sensing amplifier enable signal SEN of thesensing amplifier is activated at high level during a period C. Thus,the data of the bitline is (referring to the bitline of the MC and thebitline of the reference cell RC) is amplified.

[0079] At this time, the plate line P/L and the reference wordlineREF_W/L are maintained at high level and then transited low level when aperiod D starts. A high pulse of column selector CS is received inperiod D so that the external data of the bitline B/L is sent to thedata bus DB.

[0080] In period E, W/L is high while P/L remains low, so that datahaving a logic value of “1” is written in the main cell MC.

[0081] Finally, it is noted that the plate line P/L and reference plateline REF_P/L are not transited when the wordline W/L and the referencewordline REF_W/L are transited. Accordingly, interference noise that mayoccur due to simultaneous transition of the plate line P/L and thewordline W/L or the reference wordline REF_W/L and the reference plateline REF_P/L can be avoided.

[0082] Afterwards, the amplification operation of the sensing amplifierproceeds to a stable mode.

[0083] The operation of the read mode will now be described withreference FIG. 10.

[0084] In the read mode, the data of the bitline is transmitted to thedata bus. The read mode operations is implemented with timing such asthe timing of the write mode. Data of the cell in the period B has alogic value of “0” and is amplified in period C. Column selector CS isactivated to a high level period D . At this time, the data of the maincell MC is output to the sensing amplifier S/A and the previous datahaving a logic value of “1” is restored in the main cell MC duringperiod E.

[0085] In other words, a precharge period starts if the external chipenable signal CSBpad is transited to high level. Then, the wordline W/Lis orly transited from low level to high level during a period E. Atthis time, since the sensing amplifier enable signal SEN is continuouslymaintained at high level to activate the sensing amplifier, the bitlineB/L continuously maintains amplified data or reprogrammed data.

[0086] Accordingly, the data of the main cell having a logic value “1”,destroyed during the period B, is restored. This is called a restoringoperation.

[0087] If the restoring operation is completed, the bitline B/L and thestorage node SN of the reference cell RC are initiated at the groundvoltage level during the period F, to start the next cycle.

[0088] Next, the pulse generator 56 for detecting a weak cell using avariable charge amount stored in the ferroelectric capacitor of the maincell MC depending on the size of the restore pulse width PW1 during theread mode will be described.

[0089] As shown in FIG. 5, the pulse generator 56 includes a switchingsignal generating unit 54, which includes a first switching signalgenerator 52 and a second switching signal generator 53, and a pulsewidth variable controller 55 for selectively receiving signals SWC1 andSWC2 output from the first and second switching signal generators 52 and53 and for varying the pulse Pw1.

[0090] As shown in FIG. 11, the pulse width variable controller 55includes first, second and third PMOS transistors DP1, DP2 and DP3 and afirst NMOS transistor NM1 connected in series. An input signal INPUT isinput to the gates of the first-third PMOS transistors DP1-DP3 and thefirst NMOS transistor NM1. The first, second and third PMOS transistorsDP1, DP2 and DP3 and the first NMOS transistor NM1 are connected inseries between a power source voltage terni inal VCC and a groundvoltage terminal VSS. Fourth and fifth PMOS transistors SP1 and SP2 arerespectively connected with the first PMOS transistor DP1 and the secondPMOS transistor DP2 in parallel, and are driven by the first and secondswitching signals SWC1 and SWC2 for varying the pulse width. The pulsewidth variable controller 55 further includes a first inverter INVI forinverting a signal of a common node of the third PMOS transistor DP3 andthe first NMOS transistor NM1 to output the restore pulse PW1.

[0091] The width of the restore pulse PW1 output from the pulse widthvariable controller 55 is determined depending on the first and secondswitching signals SWC1 and SWC2.

[0092] The first and second switching signal generators 52 and 53 forgenerating the first and second switching signals SWC1 and SWC2 will nowbe described.

[0093]FIG. 12 is a circuit diagram of the first switching signalgenerator of FIG. 5, and FIG. 13 is a circuit diagram of the secondswitching signal generator of FIG. 5.

[0094] First, as shown in FIG. 12, the first switching signal generator52 includes a system power voltage sensitive divider 121, a signalsynchronizing unit 122, a level maintaining unit 123, a currentsupplying unit 124, a control unit 125, and a high voltage determiningunit 126.

[0095] The system power voltage sensitive divider 121 includes aplurality of NMOS transistors Tn1-Tnn connected in series. Each of theNMOS transistors Tn1{tilde over ()}Tnn has a gate to which the powersource voltage VCCis applied. The system power voltage sensitive divider121 supplies the system power at a constant ratio to output a powervoltage variation value to a first output terminal out1 (the nodebetween second and third NMOS transistors Tn2 and Tn3).

[0096] The signal synchronizing unit 122 synchronizes an outputvariation of the system power voltage sensitive divider 121 with a chipenable signal CE and the output first switching signal SWC1. The signalsynchronizing unit 122 includes two NMOS transistors T1 and T2 connectedin parallel between a source terminal of the last NMOS transistor Tnn ofthe divider 121 and the ground voltage terminal VSS. The chip enablesignal CE and the first switching signal SWC1 are respectively connectedto the first and second NMOS transistors T1 and T2, and pull the firstoutput terminal out1 to ground when either of the chip enable signal CEor the first switching signal SWC1 is high.

[0097] As shown in FIG. 17, the divider 121 outputs a lower outputsignal to the first output terminal out1 in a state that the externalchip enable signal CSBpad is activated and the divider 121 outputs ahigher output signal to the first output terminal out1 in a state thatthe external chip enable signal CSBpad is deactivated.

[0098] The level maintaining unit 123 includes a PMOS transistor T4,connected between the power source voltage terminal VCC and the drainterminal of an NMOS transistor T3, and an inverter INV2 for inverting asignal of a source terminal of the PMOS transistor T4 (referred to asthe second output terminal out2) and inputting it to the gate terminalof the PMOS transistor T4.

[0099] The level maintaining unit 123 maintains a high level only whenthe second output terminal out2 of a drain terminal of the NMOStransistor T3, switched depending on the output signal of the firstoutput terminal out1 of the system power sensitive divider 121, is inthe high level (i.e., first output terminal out1 is low and the NMOStransistor T3 does not pull the second output terminal to VCC). Thelevel maintaining unit 123 is not operated if the output signal of thesecond output terminal out2 is in low level.

[0100] The current supplying unit 124 includes a PMOS transistor T5connected between the power source voltage terminal VCC and the secondoutput terminal out2. The current supplying unit 124 acts to supplycurrent to the drain terminal of the NMOS transistor T3, and maintainsthe output signal of the second output terminal out2 at high level in anormal voltage state.

[0101] The control unit 125 acts to control the current supplying unit124, and includes an inverter INV3 for inverting a signal of the sourceterminal of the PMOS transistor T4 and a NAND gate N1 for performinglogic AND operation of the chip enable signal CE and the signal of theinverter INV3 and inverting the resultant value. The output of the NANDgate N1 serves as the fourth output terminal out4, which is connected tothe gate of the PMOS transistor T5 and controls the operation thereof.

[0102] An output signal of a fourth output terminal out4, the output ofthe NAND gate N1, will be at a low level when the output signal of thesecond output terminal out2 is at a low level and the chip enable signalCE is at a high level. This activates the PMOS transistor T5 of thecurrent supplying unit 124 to supply current to the second outputterminal out2.

[0103] The output signal of the second output terminal out2 can besufficiently maintained in a normal voltage state even when current issupplied to the second output terminal out2. When in a low voltageregion, the output signal of the second output terminal out2 is boostedat high level to output high data to the third output terminal out3.Accordingly, a high voltage state is detected when the switching signalSWC1 is in low level.

[0104] The high voltage determining unit 126 detects a power sourcevoltage to determine a high voltage and a normal voltage. The outputsignal of the output terminal out2 is in high level in a normal voltageregion while the output signal of the output terminal out2 is in lowlevel in a high voltage region. The normal voltage region exists whenSP1 and SP2 are turned off and as shown in FIG. 17, and is when SWC1 andSWC2 become high. The high voltage regions occurs when either SP1 or SP2is turned on as either SWC1 or SWC2 becomes low, as shown in FIG. 17.

[0105] The high voltage determining unit 126 includes an NMOS transistorT3 and two inverters INV4 and INV5. The NMOS transistor T3 is connectedbetween the source terminal of the PMOS transistor T4 and the groundvoltage terminal VSS, and its level is determined in response tovariation of the output signal of the first output terminal out1 of thesystem power sensitive divider 121. The two inverters INV4 and INV5 areserially connected with each other to delay the signal of the drainterminal of the NMOS transistor T3.

[0106] As shown in FIG. 13, the switching signal generator 53 has thesame structure as the first switching signal generator 52 except thatthe divider 121 has been replaced with a system power voltage divider131. The system power voltage divider 131 is similar to the system powervoltage divider 121 and includes a plurality of NMOS transistors Tn1 -Tnn. However, the first and second NMOS transitors Tn1 and Tn2 areconnected to the power source voltage terminal Vcc by a diode connectorwhile the other NMOS transistors Tn3 - Tnn are connected to one anotherin series having a gate to which the power source voltage is applied.

[0107] The aforementioned switching signal generators 52 and 53 controlthe fourth and fifth PMOS transistors SP1 and SP2 (see FIG. 11) of thepulse width variable controller 55 so as to generate the first andsecond switching signals SWC1 and SWC2 for controlling the pulse widthPW1.

[0108] As shown in FIGS. 11 and 17, when the system power voltage isnormal, switching signals SWC1 and SWC2 are in high level so the fourthand fifth PMOS transistors SP1 and SP2 are turned off.. When the systempower is high, switching signals SWC1 and SWC2 are in a low level sothat SP1 and SP2 are turned on. Also, the system power voltage at thepoint that switching signal SWC1 is transmitted to a low level is lowerthan the system power voltage when switching signal SWC2 is transmittedto low level. As a result, when switching signal SWC1 is in a low leveland switching signal SWC2 is in a higher level, SP1 is on while SP2 isoff.

[0109] The operation of the pulse width variable controller 55, based onthe switching signals SWC1 and SWC2 output through the aforementionedfirst and second switching signal generators 52 and 53, will now bedescribed.

[0110] As shown in FIGS. 11, 17 and 18 a-d, when a waveform of the inputsignal INPUT is as shown in FIG. 18d and the first and second switchingsignals SWC1 and SWC2 are all in low level as shown in FIG. 17, then thevoltage VCC is transferred by the third and fourth PMOS transistors SP1and SP2 and is only delayed by the third PMOS transistor DP3 because thefourth and fifth PMOS transistors SP1 and SP2 are turned on. The pulsewidth PW1 is as shown in FIG. 18b.

[0111] In FIG. 18a, INPUT refers to a signal width a pulse with PW1before the delay occurs.

[0112] When the input signal INPUT is as shown in FIG. 18a, the firstswitching signal SWC1 is in low level and the second switching signalSWC2 is in high level, the voltage VCC is only delayed by the second andthird PMOS transistor DP2 and DP3 because the fourth PMOS transistor SP1is turned on while the fifth PMOS transistor SP2 is turned off. Thepulse width PW1 as shown in FIG. 18c is thus obtained.

[0113] If either the fourth PMOS transistor SP1 or the fifth PMOStransistor SP2 is turned on, the voltage VCC is delayed by two PMOStransistors only. Accordingly, the pulse width PW1 as shown FIG. 18c,which is greater than that of FIG. 18b, is obtained.

[0114] When the input signal INPUT is as shown in FIG. 18a, and thefirst and second switching signals SWC1 and SWC2 are all in high level,the voltage VCC is delayed by the first to third PMOS transistor DP1 toDP3 because the fourth and fifth PMOS transistors SP1 and SP2 are turnedoff. Thus, pulse width PW1 as shown in FIG. 18d, which is greater thanthat of FIG. 18c, is obtained.

[0115] Also, as shown in FIGS. 11 and 18, NM1 has a relatively largesize so delay factors do not occur and pulses are generatedsimultaneously. The delay operation is only implemented by DP1, DP2,DP3, SP1, and SP2., which have relatively great delay factors. Also, thedelay is realized at the end of the pulse because the pulses aregenerated at the same point.

[0116] INPUT (pre-PW1) refers to a pulse generated in period E and isgenerated through a separate circuit different than the circuitgenerating the W/L pulse in period B.

[0117] The method for detecting the aforementioned nonvolatileferroelectric memory device will now be described.

[0118]FIG. 14 is a graph showing dependancy of memory charges accordingto the size of the pulse width PW1, FIGS. 15(a)- 15(c) show variousexamples of the pulse width PW1, and FIG. 16 shows dependency of avoltage induced to a bitline B/L according to variation of the pulsewidth PW1 in FIGS. 15(a)-15(c).

[0119] In the present invention, to ensure reliability of thenonvolatile memory chip, a weak cell is removed in advance.

[0120] A nonvolatile ferroelectric memory cell driver includes a sensingamplifier S/A arranged between adjacent top and bottom sub cell arrayssub_(d—)T and sub_B to sense the top and bottom sub cell arrays, and awordline driver 57 for driving the wordlines of the top and bottom subcell arrays. The method for detecting a weak cell using theaforementioned nonvolatile ferroelectric memory cell driver includes thesteps of selectively outputting a word e decoding signal from theX-decoder to the wordline driver 57, varying a width of the restorepulse PW1 and outputting the varied width to the wordline driver 57 todetect the weak cell of the top and bottom cell arrays, controlling data(charge amount) to be stored in a memory cell of each cell arraysimultaneously with the output of the restore pulse PW1, varying bitlinesensing levels corresponding to the controlled data, and sensing data ofa memory cell of each cell array to detect a memory cell first reached aminimum sensing level among the varied bitline sensing levels, therebydetermining a weak cell.

[0121] In other words, the restore pulse width is varied during readingoperation of the memory cell, so that charge amount (data value) storedin the ferroelectric capacitor of the memory cell is controlled. Thebitline sensing levels are varied to correspond to the controlled chargeamount (data value). A memory cell having a bitline voltage less than aminimum sensing level, which is the voltage on the reference bitlinefrom the reference cell, is determined as a weak cell and theneliminated.

[0122] The weak cell detection is implemented for all cells bysequentially inputting address signals through a wordline driver. If thebitline sensing level output through the sensing amplifier S/A is lessthan a minimum sensing level, a weak cell is detected.

[0123] The minimum sensing level corresponds to the minimum voltage foroperating the sensing amplifier S/A. For example, supposing that ΔV2 inFIG. 16 is a sensing level, ΔV2 is compared with the reference level, asshown on FIG. 16. Then, a memory cell showing ΔV1 which is less than ΔV2is determined to be a weak memory cell, and a cell showing ΔV3 isdetermined to be a normal cell.

[0124]FIG. 14 shows dependancy of charges according to the size of thepulse width PW1 in the read and write modes of the nonvoatileferroelectric memory cell. Referring to FIG. 14, charges of the datahaving a logic value “1” are varied in such a way as Q1<Q2<Q3 when thesize of the restore pulse PW1 is P1<P2<P3. At this time, P1, P2 and P3are controlled by the first and second switching signal generators 52and 53 and the pulse width variable controller 55.

[0125] FIGS. 15(a)-15(c) and 16 show variation of the pulse width PW1and variation of a voltage induced in the bitline B/L during the readmode. Referring to FIGS. 15(a)-15(c) and 16, if the pulse width PW1 isvaried in such a way as P1<P2<P3, the data stored in the cell are alsovaried. Accordingly, the bitline level is varied in such a way asV1<V2<V3.

[0126] As described above, the restore pulse width PW1 is varied tocontrol the data stored in the cell, so that the bitline sensing levelis varied. Thus, if a voltage less than a reference bitline voltage issensed, the cell is determined as a weak cell.

[0127] At this time, the restore pulse PW1 may optionally be varied by auser.

[0128] In other words, the pulse width PW1 is varied depending on theswitching signals SWC1 and SWC2 output from the first and secondswitching signal generators 52 and 53. The varied pulse width is outputto each cell array through the word e driver 57, so that the data storedin each cell is controlled. After the bitline sensing level isdetermined by the sensing amplifier S/A, a cell having a bitline voltageless than the reference bitline voltage is detected as a weak cell andthen eliminated.

[0129] As aforementioned, the nonvolatile ferroelectric memory deviceand method for detecting a weak cell using the same according to thepresent invention has the following advantages.

[0130] First, since the power source voltage detecting circuit (firstand second switching signal generators) is provided, the weak cell canbe determined and eliminated without a separate test mode. In addition,since the size of the restore pulse is varied to control the data storedin the memory cell, the weak cell can easily be determined andeliminated even if the process conditions are varied.

[0131] The invention being thus described, it will be obvious that thesame may be varied in many ways. Such variations are not to be regardedas a departure from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

What is claimed is:
 1. A nonvolatile ferroelectric memory device,comprising: a nonvolatile ferroelectric memory cell driver including atop cell array and a bottom cell array, a sensing amplifier formedbetween the top and bottom cell arrays, for sensing the top and bottomcell arrays, and a word line driver for driving a word line of the topand bottom cell arrays; an X-decoder for selectively outputting a wordline decoding signal to the wordline driver; and a pulse widthgenerating unit for varying a width of a restore pulse and outputtingthe varied width to the word line driver to detect a weak cell of thetop and bottom cell arrays.
 2. The nonvolatile ferroelectric memorydevice of claim 1, wherein the top and bottom cell arrays include areference cell provided in one bitline and a plurality of main cellsdriven by a bitline signal equal to the reference cell.
 3. Thenonvolatile ferroelectric memory device of claim 1, wherein the pulsewidth generating unit includes first and second switching signalgenerators for outputting switching control signals to vary the restorepulse width, and a pulse width variable controller for selectivelyreceiving the switching control signals of the first and secondswitching signal generators to vary the restore pulse.
 4. Thenonvolatile ferroelectric memory device of claim 3, wherein the firstswitching signal generator includes: a system power voltage sensitivedivider for descending system power at a constant ratio to output apower voltage variation through a first node; a signal synchronizingunit for synchronizing an output variation of the system power voltagesensitive divider with an external chip enable signal; a levelmaintaining unit for maintaining a relatively high level state when asecond node of a transistor switched by the first node is in arelatively high level; a current supplying unit for supplying current tothe second node to maintain the second node at a relatively high levelin a normal voltage state; a control unit for controlling the currentsupplying unit in response to the second node and the external chipenable signal; and a high voltage determining unit for detecting a levelof the second node to determine a relatively high voltage and a normalvoltage.
 5. The nonvolatile ferroelectric memory device of claim 3,wherein the second switching signal generator includes: a system powervoltage sensitive divider for descending system power at a constantratio greater than the system power of the first switching signalgenerator to output a power voltage variation through a first node; asignal synchronizing unit for synchronizing an output variation of thesystem power voltage sensitive divider with the external chip enablesignal; a level maintaining unit for maintaining a relatively high levelstate when a second node of a transistor switched by the first node isin a relatively high level; a current supplying unit for supplyingcurrent to the second node to maintain the second node at relativelyhigh level in a normal voltage state; a control unit for controlling thecurrent supplying unit in response to the second node and the externalchip enable signal; and a high voltage determining unit for detecting alevel of the second node to determine a relatively high voltage and anormal voltage.
 6. The nonvolatile ferroelectric memory device of claim4, wherein the system power voltage sensitive divider includes aplurality of NMOS transistors connected in series, a drain terminal ofthe first NMOS transistor being connected to a power source voltageterminal, and a power source voltage being applied to each gate of theNMOS transistors.
 7. The nonvolatile ferroelectric memory device ofclaim 5, wherein the system power voltage sensitive divider includes aplurality of NMOS transistors, a drain terminal of the first NMOStransistor being connected to a power source voltage terminal, and thefirst and second NMOS transistors being connected to each other inseries by a diode
 8. The nonvolatile ferroelectric memory device ofclaim 4, wherein the signal synchronizing unit receives a chip enablesignal and an output signal of the high voltage determining unit, andthe synchronizing unit includes two NMOS transistors connected inparallel between the system power voltage sensitive divider and a groundvoltage terminal.
 9. The nonvolatile ferroelectric memory device ofclaim 4, wherein the level maintaining unit includes a PMOS transistorformed between a power source voltage terminal and the second node, andan inverter for inverting a signal of the second node and inputting itto the PMOS transistor.
 10. The nonvolatile ferroelectric memory deviceof claim 4, wherein the current supplying units includes a PMOStransistor connected between a power source voltage terminal and thesecond node and switched under the control of the control unit.
 11. Thenonvolatile ferroelectric memory device of claim 4, wherein the controlunit includes an inverter for inverting a signal of the second node, anda NAND gate for performing logic AND operation of the chip enable signaland the signal of the inverter and inverting the resultant value. 12.The nonvolatile ferroelectric memory device of claim 4, wherein the highvoltage determining unit includes two inverters connected in series todelay the signal of the second node.
 13. The nonvolatile ferroelectricmemory device of claim 3, wherein the pulse width variable controllerincludes first, second and third PMOS transistors DP1, DP2 and DP3 and afirst NMOS transistor NM1 to which an input signal INPUT for delay iscommonly input, and the first, second and third PMOS transistors DP1,DP2 and DP3 and the first NMOS transistor NM1 being in parallelconnected between a power source voltage terminal and a ground voltageterminal; fourth and fifth PMOS transistors SP1 and SP2 respectivelyconnected with the first PMOS transistor DP1 and the second PMOStransistor DP2 in parallel and driven by first and second switchingsignals SWC1 and SWC2 for varying the pulse width; and an inverter forinverting a signal of a common node of the third PMOS transistor DP3 andthe first NMOS transistor NM1 to output the restore pulse PW1.
 14. Amethod for detecting a weak cell using a nonvolatile ferroelectricmemory device having a nonvolatile ferroelectric memory cell driverincluding a top cell array and a bottom cell array, a sensing amplifierfor sensing the top and bottom cell arrays, and a word line driver fordriving a wordline of the top and bottom cell arrays, the methodcomprising the steps of: selectively outputting a word line decodingsignal to the word line driver; varying a width of a restore pulse;outputting the restore pulse having a varied width to the wordlinedriver to detect a weak cell of the upper and lower cell arrays;controlling data in the form of a charge amount to be stored in a memorycell of each cell array to correspond to the size of the output restorepulse; outputting bitline sensing levels varied to correspond to thesize of the restore pulse; and sensing a memory cell that first reachesa minimum sensing level among the varied bitline sensing levels todetermine a weak cell.
 15. The method of claim 14, wherein the step ofvarying the restore pulse includes the steps of outputting first andsecond switching control signals for varying the width of the restorepulse; and varying the width of the restore pulse in response to thefirst and second switching control signals.
 16. The method of claim 15,wherein the restore pulse includes a first pulse delayed equivalent to afirst turn-on time of one PMOS transistor when the first and secondswitching control signals are all in a relatively low level, a secondpulse delayed equivalent to a second turn-on time of two PMOStransistors when either the first switching control signal or the secondswitching control signal is in a relatively high level, or a third pulsedelayed equivalent to a third turn-on time of three PMOS transistorswhen the first and second switching control signals are in a relativelyhigh level.
 17. The method of claim 15, wherein the data stored in thememory cell and controlled to correspond to the restore pulse is variedin such that a first charge amount<a second charge amount<a third chargeamount when the restore pulse is varied such that a first restorepulse<a second restore pulse<a third restore pulse.
 18. The method ofclaim 17, wherein the bitline sensing levels varied to correspond to thesize of the restore pulse are varied such that a first voltage<a secondvoltage<a third voltage when the restore pulse is varied such that afirst pulse<a second pulse<a third pulse.